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DATA SHEET
74LVC273 Octal D-type flip-flop with reset; positive-edge trigger
Product specification Supersedes data of 2003 Oct 30 2004 Mar 12
Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
FEATURES * Wide supply voltage range from 1.2 to 3.6 V * Inputs accept voltages up to 5.5 V * CMOS low power consumption * Direct interface with TTL levels * Output drive capability 50 transmission lines at 85 C * Complies with JEDEC standard no. 8-1A * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. * Specified from -40 to +85 C and -40 to +125 C. DESCRIPTION
74LVC273
The 74LVC273 is a low-voltage Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. The 74LVC273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (CP) and master reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements.
QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns. SYMBOL tPHL/tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in W) PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; VCC = supply voltage in Volts; N = total load switching outputs; (CL x VCC2 x fo) = sum of the outputs. 2. The definition is VI = GND to VCC. PARAMETER propagation delay CP to Qn propagation delay MR to Qn maximum clock frequency input capacitance power dissipation capacitance per flip-flop CONDITIONS CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V TYPICAL 4.8 4.8 230 5.0 outputs disabled; notes 1 and 2 22 ns ns MHz pF pF UNIT
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
FUNCTION TABLE See note 1. INPUT OPERATING MODES MR Reset (clear) Load `1' Load `0' Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition; = LOW-to-HIGH transition; X = don't care. ORDERING INFORMATION PACKAGE TYPE NUMBER TEMPERATURE RANGE 74LVC273D 74LVC273DB 74LVC273PW 74LVC273BQ PINNING PIN 1 2 3 4 5 6 7 8 9 10 SYMBOL MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 GND DESCRIPTION master reset input (active LOW) flip-flop output data input data input flip-flop output flip-flop output data input data input flip-flop output ground (0 V) 12 13 14 15 16 17 18 19 20 Q4 D4 D5 Q5 Q6 D6 D7 Q7 VCC -40 to +125 C -40 to +125 C -40 to +125 C -40 to +125 C PINS 20 20 20 20 PIN 11 PACKAGE SO20 SSOP20 TSSOP20 DHVQFN20 SYMBOL CP L H H CP X Dn X h l
74LVC273
OUTPUT Qn L H L
MATERIAL plastic plastic plastic plastic
CODE SOT163-1 SOT339-1 SOT360-1 SOT764-1
DESCRIPTION clock input (LOW-to-HIGH, edge-triggered) flip-flop output data input data input flip-flop output flip-flop output data input data input flip-flop output supply voltage
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
74LVC273
handbook, halfpage
MR 1
VCC 20 19 18 17 16 Q7 D7 D6 Q6 Q5 D5 D4 Q4
handbook, halfpage
MR 1 Q0 2 D0 3 D1 4 Q1 5
20 VCC 19 Q7 18 D7 17 D6 16 Q6
Q0 D0 D1 Q1 Q2 D2 D3 Q3
2 3 4 5
273
Q2 6 D2 7 D3 8 Q3 9 GND 10
MNA762
15 Q5 14 D5 13 D4 12 Q4 11 CP
GND(1)
6 7 8 9 10 Top view GND 11 CP
MNA975
15 14 13 12
(1) The die substrate is attached to this pad using conductive die attach material. It can not be used as a supply pin or input.
Fig.1 Pin configuration SO20 and (T)SSOP20.
Fig.2 Pin configuration DHVQFN20.
handbook, halfpage
CP
handbook, halfpage
11 1
C1 R
11 3 4 7 8 13 14 17 18 CP D0 D1 D2 D3 D4 D5 D6 D7 MR 1 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 2 5 6 9 12 15 16 19
MR
D0 D1 D2 D3 D4 D5 D6
3 4 7 8 13 14 17 18
1D
2 5 6 9 12 15 16 19
MNA764
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
MNA763
D7
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times in free air VCC = 1.2 to 2.7 V VCC = 2.7 to 3.6 V CONDITIONS maximum speed performance low-voltage applications MIN. 2.7 1.2 0 0 -40 0 0
74LVC273
MAX. 3.6 3.6 5.5 VCC +125 20 10
UNIT V V V V C ns/V ns/V
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO ICC, IGND Tstg Ptot Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. For SO20 packages: above 70 C derate linearly with 8 mW/K. For SSOP20 and TSSOP20 packages: above 60 C derate linearly with 5.5 mW/K. For DHVQFN20 packages: above 60 C derate linearly with 4.5 mW/K. PARAMETER supply voltage input diode current input voltage output diode current output voltage output source or sink current VCC or GND current storage temperature power dissipation per package Tamb = -40 to +125 C; note 2 VI < 0 note 1 VO > VCC or VO < 0 note 1 VO = 0 to VCC CONDITIONS - -0.5 - -0.5 - - -65 - MIN. -0.5 MAX. +6.5 -50 +6.5 50 50 100 +150 500 UNIT V mA V mA mA mA C mW
VCC + 0.5 V
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +85 C; note 1 VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = -100 A IO = -12 mA IO = -18 mA IO = -24 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 12 mA IO = 24 mA ILI ICC ICC input leakage current quiescent supply current VI = 5.5 V or GND VI = VCC or GND; IO = 0 2.7 to 3.6 2.7 3.0 3.6 3.6 2.7 to 3.6 - - - - - - - - - 0.1 0.1 5 0.2 0.4 2.7 to 3.6 2.7 3.0 3.0 VCC - 0.2 VCC - 0.5 VCC - 0.6 VCC - 0.8 - - - - - - - - 1.2 2.7 to 3.6 1.2 2.7 to 3.6 VCC 2.0 - - - - - - - - VCC (V) MIN. TYP.
74LVC273
MAX.
UNIT
V V V V V V V V V V V A A A
GND 0.8
0.55 5 10 500
additional quiescent VI =VCC - 0.6 V; supply current per IO = 0 input pin
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +125 C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = -100 A IO = -12 mA IO = -18 mA IO = -24 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 12 mA IO = 24 mA ILI ICC ICC input leakage current quiescent supply current VI = 5.5 V or GND VI = VCC or GND; IO = 0 2.7 to 3.6 2.7 3.0 3.6 3.6 2.7 to 3.6 - - - - - - - - - - - - 0.3 0.6 0.8 20 40 2.7 to 3.6 2.7 3.0 3.0 VCC - 0.3 VCC - 0.65 VCC - 0.75 VCC - 1.0 - - - - - - - - 1.2 2.7 to 3.6 1.2 2.7 to 3.6 VCC 2.0 - - - - - - - - VCC (V) MIN. TYP.
74LVC273
MAX.
UNIT
V V V V V V V V V V V A A A
GND 0.8
additional quiescent VI =VCC - 0.6 V; supply current per IO = 0 input pin
5000
Note 1. Typical values are measured at VCC = 3.3 V and Tamb = 25 C.
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
AC CHARACTERISTICS GND = 0 V; tr = tf = 2.5 ns; CL = 50 pF; RL = 500 . TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = -40 to +85 C; note 1 tPHL/tPLH propagation delay CP to Qn see Fig.5 and Fig.8 1.2 2.7 3.0 to 3.6 tPHL propagation delay MR to Qn see Fig.6 and Fig.8 1.2 2.7 3.0 to 3.6 tW clock pulse width HIGH or LOW see Fig.5 and Fig.8 1.2 2.7 3.0 to 3.6 tW master reset pulse width LOW see Fig.6 and Fig.8 1.2 2.7 3.0 to 3.6 trem removal time MR to CP see Fig.6 and Fig.8 1.2 2.7 3.0 to 3.6 tsu set-up time Dn to CP see Fig.7 and Fig.8 1.2 2.7 3.0 to 3.6 th hold time Dn to CP see Fig.7 and Fig.8 1.2 2.7 3.0 to 3.6 fmax maximum clock frequency see Fig.5 and Fig.8 1.2 2.7 3.0 to 3.6 tsk(0) skew note 3 3.0 to 3.6 - 1.5 1.5 - 1.5 1.5 - 5.0 4.0 - 5.0 4.0 - +3.0 +2.0 - 3.0 1.0 - +3.0 1.0 - 150 150 - 18 4.9 4.8(2) 18 5.2 4.8(2) - 1.8 1.2(2) - 1.7 1.2(2) - -1.0 -1.0(2) - 1.0 0.0(2) - -0.2 0.0(2) - - 230(2) - VCC (V) MIN. TYP.
74LVC273
MAX.
UNIT
- 8.4 8.2 - 8.9 8.7 - - - - - - - - - - - - - - - - - - 1.0
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
TEST CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = -40 to +125 C tPHL/tPLH propagation delay CP to Qn see Fig.5 and Fig.8 1.2 2.7 3.0 to 3.6 tPHL propagation delay MR to Qn see Fig.6 and Fig.8 1.2 2.7 3.0 to 3.6 tW clock pulse width HIGH or LOW see Fig.5 and Fig.8 1.2 2.7 3.0 to 3.6 tW master reset pulse width LOW see Fig.6 and Fig.8 1.2 2.7 3.0 to 3.6 trem removal time MR to CP see Fig.6 and Fig.8 1.2 2.7 3.0 to 3.6 tsu set-up time Dn to CP see Fig.7 and Fig.8 1.2 2.7 3.0 to 3.6 th hold time Dn to CP see Fig.7 and Fig.8 1.2 2.7 3.0 to 3.6 fmax maximum clock frequency see Fig.5 and Fig.8 1.2 2.7 3.0 to 3.6 tsk(0) Notes 1. All typical values are measured at Tamb = 25 C. 2. This typical value is measured at VCC = 3.3 V. skew note 3 3.0 to 3.6 - 1.5 1.5 - 1.5 1.5 - 5.0 4.0 - 5.0 4.0 - 3.0 2.0 - 3.0 1.0 - 3.0 1.0 - 150 150 - - - - - - - - - - - - - - - - - - - - - - - - - - VCC (V) MIN. TYP.
74LVC273
MAX.
UNIT
- 10.5 10.5 - 11.5 11.0 - - - - - - - - - - - - - - - - - - 1.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz MHz MHz ns
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
AC WAVEFORMS
74LVC273
handbook, full pagewidth
1/fmax VI CP input GND tW t PHL VOH Qn output VOL VM
MNA765
VM
VM
t PLH
VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load.
Fig.5
Clock (CP) to output (Qn) propagation delays, the clock pulse width and the maximum clock pulse frequency.
handbook, full pagewidth
VI MR input GND tW VI CP input GND t PLH VM t rem VM
Qn output
VM
MNA464
VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V.
Fig.6
Master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the master reset to clock (CP) removal time.
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
74LVC273
handbook, full pagewidth
VI CP input GND t su th VI Dn input GND VM t su th VM
VOH Qn output VOL VM
MNA767
VM = 1.5 V at VCC 2.7 V. VM = 0.5VCC at VCC < 2.7 V. VOL and VOH are typical output voltage drop that occur with the output load. The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig.7 Data set-up and hold times for the data input (Dn).
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
74LVC273
handbook, full pagewidth
VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL
MNA616
VCC 1.2 V 2.7 V 3.0 to 3.6 V Note
VI VCC 2.7 V 2.7 V
CL 50 pF 50 pF 50 pF
RL 500 (1)
VEXT tPLH/tPHL tPZH/tPHZ open open open GND GND GND tPZL/tPLZ 2 x VCC 2 x VCC 2 x VCC
500 500
1. The circuit performs better when RL = 1000 .
Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.8 Load circuitry for switching times.
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
PACKAGE OUTLINES
SO20: plastic small outline package; 20 leads; body width 7.5 mm
74LVC273
SOT163-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 JEITA EUROPEAN PROJECTION A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
8o o 0
ISSUE DATE 99-12-27 03-02-19
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
74LVC273
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 10 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 7.4 7.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.9 0.5 8 o 0
o
Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT339-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
2004 Mar 12
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
74LVC273
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c y HE vMA
Z
20
11
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
10
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 6.6 6.4 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8 o 0
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
2004 Mar 12
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
74LVC273
DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; SOT764-1 20 terminals; body 2.5 x 4.5 x 0.85 mm
D
B
A
A A1 E c
terminal 1 index area
detail X
terminal 1 index area e 2 L
e1 b 9 vMCAB wM C y1 C
C y
1 Eh 20
10 e 11
19 Dh 0
12 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.6 4.4 Dh 3.15 2.85 E (1) 2.6 2.4 Eh 1.15 0.85 e 0.5 e1 3.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT764-1 REFERENCES IEC --JEDEC MO-241 JEITA --EUROPEAN PROJECTION ISSUE DATE 02-10-17 03-01-27
2004 Mar 12
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Philips Semiconductors
Product specification
Octal D-type flip-flop with reset; positive-edge trigger
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
74LVC273
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
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Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/04/pp18
Date of release: 2004
Mar 12
Document order number:
9397 750 12969
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